In the semiconductor industry, TSMC is quite a distance ahead of its competitors. The company has been very radical and its 7nm EUV process is in mass production. While its 5nm process is some months from mass production, TSMC 3nm process is moving smoothly. At its recent investor and analyst meeting TSMC’s CEO and co-chairman, CC Wei said that its 3nm process technology research and development is very smooth. In addition, early customers are now participating in the technical definition. TSMC 3nm process will further strengthen the company’s position in the future.
At present, TSMC 3nm process is still in the early stage of development. The company has not given any technical details, as well as performance and power consumption indicators. As of now, we do not know the amount of improvement in the 3nm process relative to the 5nm process. For now, the company has only evaluated all possible transistor structure designs for the 3nm process. Furthermore, it believes that it has a very good solution with customers. The specification is still in development but TSMC is confident that it will meet all the requirements of major customers.
Samsung has previously disclosed that it will use a nano-sheet based gate-all-around MBCFET transistor structure on the 3nm process. The process node is referred to as 3GAAE. Considering that TSMC must maintain sufficient competitiveness in the new process, there will inevitably be a new architecture, technology, materials and so on. In addition, TSMC’s 5nm process uses 14 EUV EUV lithography layers, which should be used more on 3nm, but it is still possible to continue to use DUV deep UV lithography technology. TSMC previously disclosed that it plans to mass-produce its 3nm process in 2022.